1. Field of the Invention
The present invention relates generally to digital-analog converter circuits. More specifically, the invention relates to a digital-analog converter circuit that is capable of obtaining a highly accurate analog signal and that is immune to the influence of device fluctuations.
2. Description of Related Art
As an example of conventional techniques on digital-analog converter circuits, Japanese Unexamined Patent Application Publication No. 10-154937 discloses a digital-analog converter circuit using an 8-bit ladder R-2R resistance network that produces an output with a combined voltage having a binary rate corresponding to a digital input signal. FIG. 21 shows a three-bit digital-analog converter circuit using an 8-bit ladder R-2R resistance network similar to the above. Digital signals D0 to D2 are input to a decoder section 100, wherein D0 represents a lowest-order bit and D2 represents a highest-order bit. In the decoder section 100, the connection to a high-level reference voltage AVD and a low-level reference voltage AVS is switched corresponding to the digital signals D0 to D2. An analog signal voltage AV, which is in the form of a converted analog signal, is output from an output terminal AOUT. Additionally, the relation between the output code of the digital signal and the analog signal voltage AV is shown in FIG. 22A. As is shown in FIG. 22A, the analog signal voltage AV, converted into the analog signal, is output in proportion to the output code.